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ISL84782
Data Sheet November 17, 2004 FN6097.3
Ultra Low ON-Resistance, Low-Voltage, Single Supply, Differential 4 to 1 Analog Multiplexer
The Intersil ISL84782 device contains precision, bidirectional, analog switches configured as a differential 4-channel multiplexer/demultiplexer. It is designed to operate from a single +1.6V to +3.6V supply. The device has an inhibit pin to simultaneously open all signal paths. ON resistance is 0.5 with a +3V supply and 0.62 with a single +1.8V supply. Each switch can handle rail to rail analog signals. The off-leakage current is only 4nA max at +25C and 30nA max at +85C with a +3.3V supply. All digital inputs are 1.8V logic-compatible when using a single +3V supply. The ISL84782 is a differential 4 to 1 multiplexer device that is offered in a 16 Ld TSSOP package and a 16 Ld thin QFN package. Table 1 summarizes the performance of this family.
TABLE 1. FEATURES AT A GLANCE ISL84782 Configuration 3V RON 3V tON/tOFF 1.8V RON 1.8V tON/tOFF Packages Diff 4:1 Mux 0.5 16ns/13ns 0.62 24ns/16ns 16 Ld TSSOP, 16 Ld 3x3 Thin QFN
Features
* Pin Compatible Replacement for the MAX4782 and MAX4618 * ON Resistance (RON) - V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 - V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.62 * RON Matching Between Channels. . . . . . . . . . . . . . . . 0.12 * RON Flatness Across Signal Range . . . . . . . . . . . . . .0.056 * Single Supply Operation. . . . . . . . . . . . . . . . . +1.6V to +3.6V * Low Power Consumption (PD). . . . . . . . . . . . . . . . . . <0.2W * Fast Switching Action (VS = +3V) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13ns * Guaranteed Break-Before-Make * High Current Handling Capacity (300mA Continuous) * Available in 16 Ld 3x3 Thin QFN and 16 Ld TSSOP * 1.8V CMOS-Logic Compatible (+3V Supply) * Pb-Free Available (RoHS Compliant) (see Ordering Info) * ISL84782IR Replaces the ISL43L740IR.
Applications
* Battery Powered, Handheld, and Portable Equipment - Cellular/Mobile Phones - Pagers - Laptops, Notebooks, Palmtops * Portable Test and Measurement * Medical Equipment * Audio and Video Switching
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)" * Application Note AN557 "Recommended Test Procedures for Analog Switches"
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL84782 Pinouts
(Note 1) ISL84782IV (TSSOP) TOP VIEW ISL84782IR (3x3 THIN QFN) TOP VIEW
A2 A0 B2 13 12 B1 11 COMB 10 B0 9 5 N.C. 6 GND 7 ADD0 8 ADD1 B3 V+ 14
A0 1 A2 2 COMA 3 A3 4 A1 5 INH 6 N.C. 7 GND 8 LOGIC
16 V+ 15 B2 14 B1 13 COMB 12 B0 11 B3 10 ADD1 9 ADD0 COMA A3 A1 INH 1 2 3 4
16
15
NOTE: 1. Switches Shown for Logic "0" Inputs.
Truth Table
ISL84782 INH 1 0 0 0 0 ADD0 X 0 0 1 1 ADD1 X 0 1 0 1 SWITCH ON None A0, B0 A1, B1 A2, B2 A3, B3
Ordering Information
PART NO. ISL84782IV ISL84782IV-T ISL84782IR ISL84782IR-T ISL84782IVZ (See Note) ISL84782IVZ-T (See Note) FUNCTION ISL84782IRZ (See Note) ISL84782IRZ-T (See Note) TEMP. RANGE (C) -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 PACKAGE 16 Ld TSSOP 16 Ld TSSOP Tape & Reel PKG. DWG. # M16.173 M16.173
16 Ld 3x3 Thin QFN L16.3x3A 16 Ld 3x3 Thin QFN L16.3x3A Tape & Reel 16 Ld TSSOP (Pb-free) 16 Ld TSSOP Tape and Reel (Pb-free) M16.173 M16.173
NOTE: Logic "0" 0.5V. Logic "1" 1.4V, with a 3V supply. X = Don't Care.
Pin Descriptions
PIN V+ N.C. GND INH COMA COMB A0-A3 B0-B3 ADDx System Power Supply Input (1.6V to 3.6V) No Connect. Not internally connected. Ground Connection Digital Control Input. Connect to GND for Normal Operation. Connect to V+ to turn all switches off. Analog Switch Channel A Output Analog Switch Channel B Output Analog Switch Channel A Input Analog Switch Channel B Input Address Input Pin
-40 to 85 -40 to 85
16 Ld 3x3 Thin QFN L16.3x3A (Pb-free) 16 Ld 3x3 Thin QFN L16.3x3A Tape and Reel (Pb-free)
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
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ISL84782
Absolute Maximum Ratings
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.7V Input Voltages INH, Ax, Bx, ADDx (Note 2) . . . . . . . . . . . . . . -0.3 to (V+) + 0.3V Output Voltages COMx (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (V+) + 0.3V Continuous Current NO or COM . . . . . . . . . . . . . . . . . . . . . 300mA Peak Current NO or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . 500mA ESD Rating HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4kV
Thermal Information
Thermal Resistance (Typical, Note 3) JA (C/W) 16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 150 16 Ld 3x3 QFN Thin Package . . . . . . . . . . . . . . . . . 75 Maximum Junction Temperature (Plastic Package). . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300C (Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 2. Signals on Ax, Bx, COMx, ADDx, or INH exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 3V Supply Test Conditions: VSUPPLY = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 4, 8),
Unless Otherwise Specified TEST CONDITIONS TEMP (C) (NOTE 5) MIN (NOTE 5) MAX UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON
TYP
Full V+ = 2.7V, ICOM = 100mA, VAX or VBX = 0V to V+, (See Figure 5) V+ = 2.7V, ICOM = 100mA, VAX or VBX = Voltage at max RON, (Note 6) V+ = 2.7V, ICOM = 100mA, VAX or VBX = 0V to V+, (Note 7) V+ = 3.3V, VCOM = 0.3V, 3V, VAX or VBX = 3V, 0.3V 25 Full 25 Full 25 Full 25 Full 25 Full
0 -4 -30 -8 -60
0.5 0.12 0.056 -
V+ 0.75 0.8 0.2 0.2 0.15 0.15 4 30 8 60
V nA nA nA nA
RON Matching Between Channels, RON RON Flatness, RFLAT(ON)
Ax or Bx OFF Leakage Current, IAx(OFF) or IBx(OFF)
COM ON Leakage Current, ICOM(ON) V+ = 3.3V, VCOM = VAX or VBX = 0.3V, 3V
DIGITAL INPUT CHARACTERISTICS Input Voltage High, VINH, VADDH Input Voltage Low, VINL, VADDL Input Current, IINH, IINL, IADDH, IADDL V+ = 3.6V, VINH = VADD = 0V or V+ (Note 10) DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON V+ = 2.7V, VAx or VBx = 1.5V, RL = 50, CL = 35pF, (See Figure 1, Note 10) V+ = 2.7V, VAx or VBx = 1.5V, RL = 50, CL = 35pF, (See Figure 1, Note 10) V+ = 2.7V, VAX or VBX = 1.5V, RL = 50, CL = 35pF, (See Figure 1, Note 10) V+ = 3.3V, VAX or VBX = 1.5V, RL = 50, CL = 35pF, (See Figure 3, Note 10) 25 Full 25 Full 25 Full 25 Full 1 16 14 19 4 25 27 23 25 28 30 ns ns ns ns ns ns ns ns Full Full Full 1.4 -0.5 0.5 0.5 V V A
Inhibit Turn-OFF Time, tOFF
Address Transition Time, tTRANS
Break-Before-Make Time, tBBM
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FN6097.3 November 17, 2004
ISL84782
Electrical Specifications - 3V Supply Test Conditions: VSUPPLY = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 4, 8),
Unless Otherwise Specified (Continued) TEST CONDITIONS CL = 1.0nF, VG = 0V, RG = 0, (See Figure 2) f = 1MHz, VAX or VBX = VCOM = 0V, (See Figure 7) f = 1MHz, VAX or VBX = VCOM = 0V, (See Figure 7) f = 1MHz, VAX or VBX = VCOM = 0V, (See Figure 7) RL = 50, CL = 35pF, f = 100kHz, (See Figures 4 and 6) f = 20Hz to 20kHz, 0.5Vp-p, RL = 32 TEMP (C) 25 25 25 25 25 25 25 (NOTE 5) MIN (NOTE 5) MAX UNITS pC pF pF pF dB dB %
PARAMETER Charge Injection, Q Input OFF Capacitance, COFF COM OFF Capacitance, COFF COM ON Capacitance, CCOM(ON) OFF Isolation Crosstalk, (Note 9) Total Harmonic Distortion (THD)
TYP -65 62 218 232 65 -100 0.02
POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ V+ = 3.6V, VINH, VADD = 0V or V+, Switch On or Off Full 25 Full NOTES: 4. VIN = Input voltage to perform proper function. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. RON matching between channels is calculated by subtracting the channel with the highest max Ron value from the channel with lowest max Ron value. 7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 8. Parts are 100% tested at +25C. Limits across the full temperature range are guaranteed by design and correlation. 9. Between any two switches. 10. Guaranteed but not tested. 1.6 3.6 0.05 0.9 V A A
Electrical Specifications: 1.8V Supply Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1V, VINL = 0.4V (Notes 4, 8),
Unless Otherwise Specified TEST CONDITIONS TEMP (C) MIN (NOTE 5) MAX (NOTE 5) UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON
TYP
Full V+ = 1.8V, ICOM = 10.0mA, VAX or VBX = 1.0V, (See Figure 5) V+ = 1.8V, ICOM = 10.0mA, VAX or VBX = 1.0V, (See Figure 5) V+ = 1.8V, ICOM = 10.0mA, VAX or VBX = 0V, 0.9V, 1.6V, (See Figure 5) 25 Full 25 Full 25 Full
0 -
0.63 0.12 0.12 0.14 0.14
V+ 0.85 0.9 -
V
RON Matching Between Channels, RON) RON Flatness, RFLAT(ON)
DIGITAL INPUT CHARACTERISTICS Input Voltage High, VINH, VADDH Input Voltage Low, VINL, VADDL Input Current, IINH, IINL, IADDH, IADDL DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON V+ = 1.8V, VAx or VBx = 1.0V, RL = 50, CL = 35pF, (See Figure 1, Note 10) 25 Full 24 33 35 ns ns V+ = 1.8V, VINH, VADD = 0V or V+ (Note 10) Full Full Full 1 -0.5 0.4 0.5 V V A
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ISL84782
Electrical Specifications: 1.8V Supply Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1V, VINL = 0.4V (Notes 4, 8),
Unless Otherwise Specified (Continued) TEST CONDITIONS V+ = 1.8V, VAx or VBx = 1.0V, RL = 50, CL = 35pF, (See Figure 1, Note 10) V+ = 1.8V, VAX or VBX = 1.0V, RL = 50, CL = 35pF, (See Figure 1, Note 10) V+ = 1.8V, VAX or VBX = 1.0V, RL = 50, CL = 35pF, (See Figure 3, Note 10) CL = 1.0nF, VG = 0V, RG = 0, (See Figure 2) TEMP (C) 25 Full 25 Full 25 25 MIN (NOTE 5) MAX (NOTE 5) UNITS 25 27 34 36 ns ns ns ns ns pC
PARAMETER Inhibit Turn-OFF Time, tOFF
TYP 16 25 9 -39
Address Transition Time, tTRANS
Break-Before-Make Time, tBBM Charge Injection, Q
Test Circuits and Waveforms
V+ LOGIC INPUT 50% 0V tON V+ A0, B0 A1,A2,B1, B2,A3,B3 90% LOGIC INPUT INH GND ADD0-1 RL 50 CL 35pF COMA COMB VOUT tr < 5ns tf < 5ns C V+ C
VA0, VB0 SWITCH OUTPUT
90%
VOUT
0V tOFF
Logic input waveform is inverted for switches that have the opposite logic sense.
Repeat test for other switches. CL includes fixture and stray capacitance. RL -----------------------------V OUT = V (NO or NC) R + R L ( ON ) FIGURE 1B. INHIBIT tON/tOFF TEST CIRCUIT
FIGURE 1A. INHIBIT tON/tOFF MEASUREMENT POINTS
V+ LOGIC INPUT 50% 0V tTRANS
tr < 5ns tf < 5ns C
V+
C
V+ VA0, VB0 SWITCH OUTPUT 10% VA3, VB3 tTRANS
0V
A0, B0 A1,A2,B1, B2,A3,B3 ADD0-1 GND COMA, COMB INH VOUT
VOUT
90%
LOGIC INPUT
RL 50
CL 35pF
Logic input waveform is inverted for switches that have the opposite logic sense.
Repeat test for other switches. CL includes fixture and stray capacitance. RL V OUT = V (NO or NC) -----------------------------R +R
L ( ON )
FIGURE 1C. ADDRESS tTRANS MEASUREMENT POINTS
FIGURE 1D. ADDRESS tTRANS TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
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FN6097.3 November 17, 2004
ISL84782 Test Circuits and Waveforms (Continued)
V+ C
V+ LOGIC INPUT OFF ON 0V 0 SWITCH OUTPUT VOUT Q = VOUT x CL VOUT VG ADD1 ADD0 CHANNEL SELECT GND OFF RG VOUT Ax, Bx COMA, COMB
INH LOGIC INPUT
CL 1000pF
FIGURE 2A. Q MEASUREMENT POINTS
Repeat test for other switches. FIGURE 2B. Q TEST CIRCUIT FIGURE 2. CHARGE INJECTION
V+ C tr < 5ns tf < 5ns V+
C
V+ LOGIC INPUT 0V
A0-A3 B0-B3 ADD0-1
COMA COMB
VOUT RL 50 CL 35pF
SWITCH OUTPUT VOUT
90%
LOGIC INPUT GND INH
0V
tBBM
Repeat test for other switches. CL includes fixture and stray capacitance. FIGURE 3B. tBBM TEST CIRCUIT
FIGURE 3A. tBBM MEASUREMENT POINTS
FIGURE 3. BREAK-BEFORE-MAKE TIME
V+
10nF V+ C
SIGNAL GENERATOR
Ax or Bx
RON = V1/100mA Ax or Bx 0V or V+ ADD1 ADD0 CHANNEL SELECT VX 100mA V1 COMA or COMB GND ADD1 ADD0 INH 0V or V+ CHANNEL SELECT
ANALYZER RL
COMx
GND
INH
Off-Isolation is measured between COM and "Off" NO terminal on each switch. Signal direction through switch is reversed and worst case values are recorded. FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. RON TEST CIRCUIT
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FN6097.3 November 17, 2004
ISL84782 Test Circuits and Waveforms (Continued)
V+ C V+ C
SIGNAL GENERATOR
Ax 0V or V+ CHANNEL SELECT
50 COMA Ax or Bx
ADD1 ADD0 Bx N.C.
IMPEDANCE ANALYZER
ADD1 ADD0 COMA or COMB GND INH
0V or V+
CHANNEL SELECT
ANALYZER RL
COMB
GND
INH
Crosstalk is measured between adjacent channels with one channel ON and the other channel OFF. Signal direction through switch is reversed and worst case values are recorded. FIGURE 6. CROSSTALK TEST CIRCUIT FIGURE 7. CAPACITANCE TEST CIRCUIT
Detailed Description
The ISL84782 analog multiplexer offers precise switching capability from a single 1.6V to 3.6V supply with low onresistance (0.5) and high speed operation (tON = 16ns, tOFF = 13ns). The device is especially well suited for portable battery powered equipment thanks to the low operating supply voltage (1.6V), low power consumption (0.2W), low leakage currents (60nA max). High frequency applications also benefit from the wide bandwidth, and the very high off isolation and crosstalk rejection.
additional diodes limit the analog signal from 1V below V+ to 1V above GND. The low leakage current performance is unaffected by this approach, but the switch signal range is reduced and the resistance may increase, especially at low supply voltages.
OPTIONAL PROTECTION RESISTOR FOR LOGIC INPUTS 1k 1k
OPTIONAL PROTECTION DIODE V+ ADDX INH VNOx VCOM
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to GND (see Figure 8). To prevent forward biasing these diodes, V+ must be applied before any input signals, and the input signal voltages must remain between V+ and GND. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1k resistor in series with the input (see Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not applicable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low RON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see Figure 8). These
GND OPTIONAL PROTECTION DIODE
FIGURE 8. OVERVOLTAGE PROTECTION
Power-Supply Considerations
The ISL84782 construction is typical of most CMOS analog switches, in that it has two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set its analog voltage limits. Unlike switches with a 4V maximum supply voltage, the ISL84782 4.7V maximum supply voltage provides plenty of room for the 10% tolerance of 3.6V supplies, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 1.6V but the part will operate with a supply below 1.5V. It is important to note that the input signal range, switching times, and on-
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FN6097.3 November 17, 2004
ISL84782
resistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance curves for details. V+ and GND power the internal logic (thus setting the digital switching point) and level shifters. The level shifters convert the logic levels to switched V+ and V- signals to drive the analog switch gate terminals. amount of feed through from one switch to another. Figure 18 details the high Off Isolation and Crosstalk rejection provided by this family. At 100kHz, Off Isolation is about 65dB in 50 systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease Off Isolation and Crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance.
Logic-Level Thresholds
This device is 1.8V CMOS compatible (0.5V and 1.4V) over a supply range of 2.0V to 3.6V (see Figure 13). At 3.6V the VIH level is about 1.27V. This is still below the 1.8V CMOS guaranteed high output minimum level of 1.4V, but noise margin is reduced. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation.
Leakage Considerations
Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND. Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and V+ or GND.
High-Frequency Performance
In 50 systems, signal response is reasonably flat even past 10MHz with a -3dB bandwidth of 70MHz (see Figure 17). The frequency response is very consistent over a wide V+ range, and for varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed through from a switch's input to its output. Off Isolation is the resistance to this feed through, while Crosstalk indicates the
Typical Performance Curves TA = 25C, Unless Otherwise Specified
0.75 V+ = 1.65V 0.7 0.65 0.55 RON () RON () 0.6 0.55 0.5 0.45 0.4 V+ = 2.7V V+ = 3V V+ = 3.6V 0.35 0 1 2 VCOM (V) 3 4 0 0.5 1 1.5 VCOM (V) 2 2.5 3 V+ = 1.8V 0.5 25C 85C ICOM = 100mA 0.6 0.65 V+ = 3V ICOM = 100mA
0.45
0.4 -40C
FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE
FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE
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FN6097.3 November 17, 2004
ISL84782 Typical Performance Curves TA = 25C, Unless Otherwise Specified (Continued)
0.75 0.7 0.65 0.6 0.55 0.5 0.45 -40C 0.4 0 0.5 1 VCOM (V) 1.5 2 Q (pC) -10 V+ = 1.8V ICOM = 100mA -20 -30 85C -40 -50 -60 -70 -80 -90 -100 -110 0 0.5 1 1.5 VCOM (V) 2 2.5 3 V+ = 3V V+ = 1.8V
RON ()
25C
FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE
1.6
60
1.4 50 1.2 tRANS (ns) VINL VINH 1 40
VINH AND VINL (V)
30 85C 20 25C
0.8
0.6
-40C
10 1 1.5 2 2.5 V+ (V) 3 3.5 4 4.5
1
1.5
2
2.5 3 V+ (V)
3.5
4
4.5
FIGURE 13. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
FIGURE 14. ADDRESS TRANS TIME vs SUPPLY VOLTAGE
60
25
50 20 tOFF (ns) tON (ns) 40 85C 25C 15 -40C 20 -40C
30
85C
25C
10
10 1 1.5 2 2.5 3 V+ (V) 3.5 4 4.5
1
1.5
2
2.5 V+ (V)
3
3.5
4
4.5
FIGURE 15. INHIBIT TURN - ON TIME vs SUPPLY VOLTAGE
FIGURE 16. INHIBIT TURN - OFF TIME vs SUPPLY VOLTAGE
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FN6097.3 November 17, 2004
ISL84782 Typical Performance Curves TA = 25C, Unless Otherwise Specified (Continued)
NORMALIZED GAIN (dB) V+ = 3V 0 -10 GAIN 0 V+ = 3V -10 -20 -30 PHASE 0 20 40 60 80 RL = 50 VIN = 0.2VP-P to 2VP-P 0.1 1 10 FREQUENCY (MHz) PHASE (DEGREES) CROSSTALK (dB) -40 -50 ISOLATION -60 -70 -80 CROSSTALK -90 -100 1k 10k 100k 1M 10M 100 110 100M 500M 70 80 90 20 30 OFF ISOLATION (dB) 40 50 60 10
100 100
FREQUENCY (Hz)
FIGURE 17. FREQUENCY RESPONSE
FIGURE 18. CROSSTALK AND OFF ISOLATION
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP): GND (QFN Paddle Connection: To Ground or Float) TRANSISTOR COUNT: 228 PROCESS: Submicron CMOS
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FN6097.3 November 17, 2004
ISL84782 Thin Shrink Small Outline Plastic Packages (TSSOP)
N INDEX AREA E E1 -B1 2 3 L 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 GAUGE PLANE 0.25(0.010) M BM
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.033 0.0075 0.0035 0.193 0.169 MAX 0.043 0.006 0.037 0.012 0.008 0.201 0.177 MILLIMETERS MIN 0.05 0.85 0.19 0.09 4.90 4.30 MAX 1.10 0.15 0.95 0.30 0.20 5.10 4.50 NOTES 9 3 4 6 7 8o Rev. 1 2/02
A1 0.10(0.004) A2 c
E1 e E L N
e
b 0.10(0.004) M C AM BS
0.026 BSC 0.246 0.020 16 0o 8o 0.256 0.028
0.65 BSC 6.25 0.50 16 0o 6.50 0.70
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AB, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
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FN6097.3 November 17, 2004
ISL84782 Thin Quad Flat No-Lead Plastic Package (TQFN) Thin Micro Lead Frame Plastic Package (TMLFP)
)
2X 0.15 C A A 9 D1 D1/2 6 INDEX AREA N 1 2 3 E1/2 E1 9 2X 0.15 C B 2X 0.15 C A 4X 0 TOP VIEW A2 A / / 0.10 C 0.08 C SEATING PLANE SIDE VIEW NX b 4X P D2 (DATUM B) 4X P 1 (DATUM A) 6 INDEX AREA NX L Ne 8 (Nd-1)Xe REF. BOTTOM VIEW A1 NX b 5 2 3 E2 7 E2/2 8 (Ne-1)Xe REF. D2 2N 5 0.10 M C A B 7 8 NX k A3 A1 B E/2 E 2X 0.15 C B D D/2
L16.3x3A
16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L N Nd Ne P 1.35 0.20 0.30 1.35 0.18 MIN 0.70 NOMINAL 0.75 0.20 REF 0.23 3.00 BSC 2.75 BSC 1.50 3.00 BSC 2.75 BSC 1.50 0.50 BSC 0.40 16 4 4 0.60 12 0.50 1.65 1.65 0.30 MAX 0.80 0.05 0.80 NOTES 9 9 5, 8 9 7, 8, 10 9 7, 8, 10 8 2 3 3 9 9 Rev. 0 6/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance.
C
9
9 CORNER OPTION 4X
SECTION "C-C" C L C L
8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.
L1 e 10 L
L1 CC e
10
L
9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Compliant to JEDEC MO-220WEED-2 Issue C, except for the E2 and D2 MAX dimension.
TERMINAL TIP FOR EVEN TERMINAL/SIDE
FOR ODD TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN6097.3 November 17, 2004

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